The present invention relates to a counter circuit and, more particularly, to a counter circuit for outputting a detection signal when an input signal to be counted occurs a plurality of times at which the count of the input signal becomes at a count value.
Such a counter circuit is composed, in general, of a register temporarily storing a count value of the predetermined time and a counter stage counting the input signal to the count value inputted from the register to produce the detection signal. As the count stage, there are known two types, one of which employs a down-counter and the other of which employs an up-counter. In the counter stage employing the down-counter, the count value from the register is preset into the down-counter in response to an initial signal and the count value of the down-counter is decremented one by one each time the count signal is applied. When the count value of the down-counter becomes zero, the detection signal is produced therefrom. In the counter stage employing the up-counter, on the other hand, the up-counter is reset to zero in response to the initial signal and the count value of the up counter is incremented one by one each time the count signal is applied. When the count value of the up-counter reaches the count value which is set by the register, the detection signal is produced.
However, the above conventional counter circuit has a drawback that the occurrence time number of the input signal to produce the detection signal cannot be controlled so long as the register stores the same count value. In other words, the count value to be stored into the register should be changed each time the counter circuit starts to count for producing the detection signal in different occurrence time number of the input signal.